For the replacement of conventional hard disks by NAND EEPROMs, a very high density and a high programming speed are required. Besides hard disks, such NAND EEPROMs has been also used for mass storage media of electronic products such as a digital camera, a portable handy terminal and the like. An increased density of EEPROMs can be achieved by using multi-level memory cells. The EEPROMs may operate with low-consumption power. In case that EEPROMs are used as mass storage media, memory per-bit cost of the EEPROM should be further reduced.
A technique for significantly reducing the memory per-bit cost of flash EEPROM device has been disclosed in ISSCC TECHNICAL DIGEST, 1995, pp 132.about.133, "A Multilevel-Cell 32Mb Flash Memory". This flash EEPROM has multi-level memory cells, programmed voltages of each which can be several threshold voltages possible to represent two bits of information, i.e., "00", "01", "10" and "11". For example, "00", "01", "10" and "11" corresponds to threshold voltages of 2.5 V!, 1.5 V!!, 0.5 V! and -3 V!, respectively. Thus, a programmed cell has one of the four threshold voltages.
However, since the above conventional flash EEPROM device requires a relatively high program voltage to achieve four threshold voltages per two bits, as compared with an EEPROM device capable of operating with two threshold voltages per two bits, and programming pulses corresponding to the four threshold voltages are sequentially supplied to word lines, a total programming time is lengthened. This causes the programming speed of the conventional EEPROM device to be lowered.
In order to implement EEPROM cells with multilevel, one of most important matters is to achieve a very narrow threshold voltage distribution per each threshold voltage level. For this reason, a technique for reducing a unit program pulse width and an incremental amount of programming voltage by using trapezoidal pulse has been disclosed in Symp. VLSI Technology Dig. Tech. Papers, 1995, pp 129.about.130, entitled "Fast and Accurate Programming Method for Multi-level NAND EEPROMs". A technique for reducing an incremental amount of programming voltages by using staircase program pulse has been also disclosed in ISSCC Dig. Tech. Papers, 1996, "A 3.3V 128 Mb Multi-level NAND Flash Memory for Mass Storage Applications". Since these flash memories has, however, relatively many in the number of program pulses and the number of incremental steps to those of EEPROM device with two levels per two bits, there is a problem that the total programming time is lengthened. Particularly, due to a relatively increased program voltage and the lengthened programming time, it is difficult to achieve threshold voltages of program inhibited cell within a given distribution boundary of each threshold voltage level.